View IDT8T49N205I_9027873.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet idt8t49n205anlgi revision b july 9, 2013 1 ?2013 integrated device technology, inc. femtoclock ? ng universal frequency translator with phase build-out IDT8T49N205I general description the IDT8T49N205I is a highly flexible femtoclock? ng general purpose, low phase noise frequency translator / synthesizer with phase build-out (pbo) suitable for networking and communications applications. it is able to generate any output frequency in the 0.98mhz - 312.5mhz range and mo st output frequencies in the 312.5mhz - 1,300mhz range (see table 3 for details). a wide range of input reference clocks and a range of low-cost fundamental mode crystal frequencies may be used as the source for the output frequency. the IDT8T49N205I has three operating modes to support a very broad spectrum of applications: 1 frequency synthesizer ? synthesizes output frequencie s from a 16mhz - 40mhz fundamental mode crystal. ? fractional feedback division is used, so there are no requirements for any specific crystal frequency to produce the desired output frequency with a high degree of accuracy. 2) high-bandwidth frequency translator ? applications: pci express, computing, general purpose ? translates any input clock in the 16mhz - 710mhz frequency range into any supported output frequency. ? this mode has a high pll loop bandwidth in order to track input reference changes, such as spread-spectrum clock modulation, so it will not attenuate much jitter on the input reference. 3) low-bandwidth frequency translator ? applications: networking & communications. ? translates any input clock in the 8khz -710mhz frequency range into any supported output frequency. ? this mode supports pll loop bandwidths in the 10hz - 580hz range and makes use of an external crystal to provide significant jitter attenuation. this device provides two factory-programmed default power-up configurations burned into one-time programmable (otp) memory. the configuration to be used is se lected by the config pin. the two configurations are specified by th e customer and are programmed by idt during the final test phase from an on-hand stock of blank devices. the two configurations may be completely independent of one another. one usage example might be to install the device on a line card with two optional daughter cards: an oc-12 option requiring a 622.08mhz lvds clock translated from a 19.44 mhz input and a gigabit ethernet option requiring a 125mhz lvpecl clock translated from the same 19.44mhz input reference. to implement other configurations , these power-up default settings can be overwritten after power-up using the i 2 c interface and the device can be completely reconfigured. however, these settings would have to be re-written next time the device powers-up. features ? fourth generation femtoclock? ng technology ? universal frequency translator/frequency synthesizer ? zero ppm frequency translation ? two outputs, individually programmable as lvpecl or lvds ? both outputs may be set to use 2.5v or 3.3v output levels ? programmable output frequency: 0.98mhz up to 1,300mhz ? two differential inputs support the following input types: lvpecl, lvds, lvhstl, hcsl ? input frequency range: 8khz - 710mhz ? phase build-out minimizes output phase change on switchover ? crystal input frequency range: 16mhz - 40mhz ? two factory-set register configurations for power-up default state ? power-up default configurati on pin or register selectable ? configurations customized via one-time programmable rom ? settings may be overwritten after power-up via i 2 c ? i 2 c serial interface for register programming ? rms phase jitter at 155.52mhz, using a 40mhz crystal (12khz - 20mhz): 378fs (typical ), low bandwidth mode (fracn) ? output supply voltage modes: v cc /v cca /v cco 3.3v/3.3v/3.3v 3.3v/3.3v/2.5v 2.5v/2.5v/2.5v ? -40c to 85c ambient operating temperature pin assignment 1 2 3 4 5 6 7 8 9 10 31 32 33 34 35 36 37 38 39 40 20 19 18 17 16 15 14 13 12 11 30 29 28 27 26 25 24 23 22 21 xtal_in xtal_out v cc clk_sel clk0 nclk0 v cc v ee clk1 nclk1 nc nc s_a0 s_a1 config sclk sdata v cc pll_bypass nc lock_ind v cc v ee oe0 q0 nq0 v cco q1 nq1 oe1 clk_active nc v ee v cca holdover clk0bad xtalbad clk1bad lf1 lf0 IDT8T49N205I 40 lead vfqfn 6mm x 6mm x 0.925mm epad 4.65mm x 4.65mm nl package top view
idt8t49n205anlgi revision b july 9, 2013 2 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out complete block diagram
idt8t49n205anlgi revision b july 9, 2013 3 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out pin descriptions and characteristics table 1. pin descriptions number name type description 1 2 xtal_in xtal_out input crystal oscillator interface designed for 12pf parallel resonant crystals. xtal_in (pin 1) is the input and xtal_out (pin 2) is the output. 3, 7, 13, 29 v cc power core supply pins. all must be either 3.3v or 2.5v. 4 clk_sel input pulldown input clock select. se lects the active differential clock input. lvcmos/lvttl interface levels. 0 = clk0, nclk0 (default) 1 = clk1, nclk1 5 clk0 input pulldown non-inverting differential clock input. 6nclk0input pullup/ pulldown inverting differential clock input. v cc /2 default when left floating (set by the internal pullup and pulldown resistors). 8, 21, 35 v ee power negative supply pins. 9 clk1 input pulldown non-inverting differential clock input. 10 nclk1 input pullup/ pulldown inverting differential clock input. v cc /2 default when left floating (set by the internal pullup and pulldown resistors). 11, 19, 20, 32 nc unused no connect. these pins are to be left unconnected. 12 pll_bypas s input pulldown bypasses the vcxo pll. in bypass mode, outputs are clocked off the falling edge of the input reference. lvcmos/lvttl interface levels. 0 = pll mode (default) 1 = pll bypassed 14 sdata i/o pullup i 2 c data input/output. open drain. 15 sclk input pullup i 2 c clock input. lvcmos/lvttl interface levels. 16 config input pulldown configuration pin. selects between one of two factory programmable pre-set power-up default configurations . the two configurations can have different output/input frequency translation ratios, different pll loop bandwidths, etc. these default configur ations can be overwritten after power-up via i 2 c if the user so desires. lvcmos/lvttl interface levels. 0 = configuration 0 (default) 1 = configuration 1 17 s_a1 input pulldown i 2 c address bit 1. lvcmos/lvttl interface levels. 18 s_a0 input pulldown i 2 c address bit 0. lvcmos/lvttl interface levels. 22 oe1 input pullup active high output enable for q1, nq 1. lvcmos/lvttl interface levels. 0 = output pins high-impedance 1 = output switching (default) 23, 24 nq1, q1 output differential outp ut pair. output type is programmable to lvds or lvpecl interface levels. 25 v cco power output supply pins for q1, nq1 and q0, nq0 outputs. eith er 2.5v or 3.3v. 26, 27 nq0, q0 output differential outp ut pair. output type is programmable to lvds or lvpecl interface levels. 28 oe0 input pullup active high output enable for q0, nq 0. lvcmos/lvttl interface levels. 0 = output pins high-impedance 1 = output switching (default) 30 lock_ind output lock indicator - indicates that the pll is in a locked condition. lvcmos/lvttl interface levels.
idt8t49n205anlgi revision b july 9, 2013 4 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics 31 clk_active output indicates which of the two differential clock inputs is currently selected. lvcmos/lvttl interface levels. 0 = clk0, nclk0 differential input pair 1 = clk1, nclk1 differential input pair 33, 34 lf0, lf1 analog i/o loop filter connection no de pins. lf0 is the output. lf1 is the input. 36 v cca power analog supply voltage. see applications section for details on how to connect this pin. 37 holdover output alarm output reflecting if the device is in a holdover state. lvcmos/lvttl interface levels. 0 = device is locked to a valid input reference 1 = device is not locked to a valid input reference 38 clk0bad output alarm output reflecting the state of clk0. lvcmos/lvttl interface levels. 0 = input clock 0 is swit ching within specifications 1 = input clock 0 is out of specification 39 clk1bad output alarm output reflecting the state of clk1. lvcmos/lvttl interface levels. 0 = input clock 1 is swit ching within specifications 1 = input clock 1 is out of specification 40 xtalbad output alarm output reflecting the state of xtal. lvcmos/lvttl interface levels. 0 = crystal is switching within specifications 1 = crystal is out of specification symbol parameter test conditio ns minimum typical maximum units c in input capacitance 3.5 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? number name type description
idt8t49n205anlgi revision b july 9, 2013 5 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out functional description the IDT8T49N205I is designed to provide two copies of almost any desired output frequency within it s operating range (0.98 - 1300mhz) from any input source in the operating range (8khz - 710mhz). it is capable of synthesizing frequencies from a crystal or crystal oscillator source. the output fre quency is generated regardless of the relationship to the input frequency. the output frequency will be exactly the required frequency in most cases. in most others, it will only differ from the desired frequency by a few ppb. idt configuration software will indicate the frequency error, if any. the IDT8T49N205I can translate the desired output frequency from one of two input clocks. again, no relationship is required between the input and output frequencies in order to translate to the output clock rate. in this frequency translation mode, a low-bandwidth, jitter attenuation option is available that makes use of an external fixed-frequency crystal or crystal oscillator to translate from a noisy input source. if the input clock is known to be fairly clean or if some modulation on the input needs to be tracked, then the high-bandwidth frequency translation mode can be used, without the need for the external crystal. the input clock references and crystal input are monitored continuously and appropriate al arm outputs are raised both as register bits and hard-wired pins in the event of any out-of-specification conditions arisin g. clock switching is supported in manual, revertive & non-revertive modes. the IDT8T49N205I has two factory- programmed configurations that may be chosen from as the default op erating state after reset. this is intended to allow the same device to be used in two different applications without any need for access to the i 2 c registers. these defaults may be over-written by i 2 c register access at any time, but those over-written settings will be lost on power-down. please contact idt if a specific set of power-up default settings is desired. configuration selection the IDT8T49N205I comes with tw o factory-programmed default configurations. when the device comes out of power-up reset the selected configuration is loaded into operating registers. the IDT8T49N205I uses the state of the config pin or config register bit (controlled by the cfg_pin_reg bit) to determine which configuration is active. when the ou tput frequency is changed either via the config pin or via internal registers, the output behavior may not be predictable during the regi ster writing and output settling periods. devices sensitive to glitches or runt pulses may have to be reset once reconfiguration is complete. once the device is out of reset, the contents of the operating registers can be modified by write access from the i 2 c serial port. users that have a custom configuration programmed may not require i 2 c access. it is expected that the idt8t49n2 05i will be used almost exclusively in a mode where the selected confi guration will be used from device power-up without any changes duri ng operation. for example, the device may be designed into a communications line card that supports different i/o modules such as a standard oc-12 module running at 622.08mhz or a (255/237) fec rate oc-12 module running at 669.32mhz. the different i/o modules would result in a different level on the config pin which would select different divider ratios within the IDT8T49N205I for the two different card configurations. access via i 2 c would not be necessary for operation using either of the internal configurations. operating modes the IDT8T49N205I has three operating modes which are set by the mode_sel[1:0] bits. there are two frequency translator modes - low bandwidth and high bandwidth and a frequency synthesizer mode. the device will operate in the same mode regardless of which configuration is active. please make use of idt-provided configuration applications to determine the best operating settings for the desired configurations of the device. output dividers & supported output frequencies in all 3 operating modes, the output stage behaves the same way, but different operating frequencies can be specified in the two configurations. the internal vco is capable of operating in a range anywhere from 1.995ghz - 2.6ghz. it is necessary to choose an integer multiplier of the desired output frequency that results in a vco operating frequency within that range. the output divider stage n[10:0] is limited to selection of integers from 2 to 2046. please refer to table 3 for the values of n applicable to the desired output frequency. table 3. output divider settings & frequency ranges register setting frequency divider minimum f out maximum f out nn[10:0] n (mhz) (mhz) 0000000000x 2 997.5 1300 00000000010 2 997.5 1300 00000000011 3 665 866.7 00000000100 4 498.75 650 00000000101 5 399 520 0000000011x 6 332.5 433.3 0000000100x 8 249.4 325 0000000101x 10 199.5 260 ... even n 1995 / n 2600 / n 1111111111x 2046 0.98 1.27
idt8t49n205anlgi revision b july 9, 2013 6 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out frequency synthesizer mode this mode of operation allows an arbitrary output frequency to be generated from a fundamental mode crystal input. for improved phase noise performance, the crystal input frequency may be doubled. as can be seen from the block diagram in figure 1, only the upper feedback loop is used in this mode of operation. it is recommended that clk0 and clk1 be left unused in this mode of operation. the upper feedback loop supports a delta-sigma fractional feedback divider. this allows the vco operating frequency to be a non-integer multiple of the crystal frequency. by using an integer multiple only, lower phase noise jitter on the output can be achieved, however the use of the delta-sigma divider logic will provide excellent performance on the output if a fractional divisor is used. figure 1. frequency synthesizer mode block diagram high-bandwidth frequency translator mode this mode of operation is used to translate one of two input clocks of the same nominal frequency into an output frequency with little jitter attenuation. as can be seen from the block diagram in figure 2, similarly to the frequency synthesizer mode, only the upper feedback loop is used. figure 2. high bandwidth frequency translator mode block diagram the input reference frequency range is now extended up to 710mhz. a pre-divider stage p is needed to keep the operating frequencies at the phase detector less than 100mhz. low-bandwidth frequency translator mode as can be seen from the block diagram in figure 3, this mode involves two pll loops. the lower loop with the large integer dividers is the low bandwidth loop and it se ts the output-to-input frequency translation ratio.this loop drives the upper dcxo loop (digitally controlled crystal oscillator) via an analog-digital converter. figure 3. low bandwidth frequency translator mode block diagram the pre-divider stage is used to sc ale down the input frequency by an integer value to achieve a frequency in this range. by dividing down the fed-back vco operating frequency by the integer divider m1[16:0] to as close as possible to the same frequency, exact output frequency translations can be achieved. for improved phase noise performance, the crystal input frequency may be doubled. the phase detector of the lower loop is desi gned to work with frequencies in the 8khz - 16khz range. for improved phase noise performance, the crystal input frequency may be doubled. alarm conditions & status bits the IDT8T49N205I monitors a number of conditions and reports their status via both output pins and register bits. all alarms will behave as indicated below in all modes of operation, but some of the conditions monitored have no valid meaning in some operating modes. for example, the status of clk0bad, clk1bad and clk_active are not relevant in frequency synthesizer mode. the outputs will still be active and it is left to the user to determine which to monitor and how to respond to them based on the known operating mode. clk_active - indicates which input clock reference is being used to derive the output frequency. lock_ind - this status is asserted on the pin & register bit when the pll is locked to the appropriate input reference for the chosen mode of operation. the status bit will not assert until frequency lock has been achieved, but will de-assert once lock is lost.
idt8t49n205anlgi revision b july 9, 2013 7 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out xtalbad - indicates if valid edges are being received on the crystal input. detection is performed by comparing the input to the feedback signal at the upper loop?s phase / frequency detector (pfd). if three edges are received on the feedback without an edge on the crystal input, the xtalbad alarm is asserted on the pin & register bit. once an edge is detected on the crystal in put, the alarm is immediately deasserted. clk0bad - indicates if valid edges are being received on the clk0 reference input. detection is performed by comparing the input to the feedback signal at the appropriate phase / frequency detector (pfd). when operating in high-bandwidth mode, the feedback at the upper pfd is used. in low-bandwidth mode, the feedback at the lower pfd is used. if three edges are received on the feedback without an edge on the divided down (p) clk0 reference input, the clk0bad alarm is asserted on the pin & register bit. once an edge is detected on the clk0 reference input, the alarm is deasserted. clk1bad - indicates if valid edges are being received on the clk1 reference input. behavior is as indicated for the clk0bad alarm, but with the clk1 input being monito red and the clk1bad output pin & register bits being affected. holdover - indicates that the device is not locked to a valid input reference clock. this can occur in manual switchover mode if the selected reference input has gone bad, even if the other reference input is still good. in automatic mode, this will only assert if both input references are bad. input reference select ion and switching when operating in frequency synthesizer mode, the clk0 and clk1 inputs are not used and the contents of this section do not apply. except as noted below, when operating in either high or low bandwidth frequency translator mode, the contents of this section apply equally when in either of those modes. both input references clk0 and clk1 must be the same nominal frequency. these may be driven by any type of clock source, including crystal oscillator modules. a difference in frequency may cause the pll to lose lock when switching between input references. please contact idt for the exact limits for your situation. the global control bits auto_man[1 :0] dictate the order of priority and switching mode to be used between the clk0 and clk1 inputs. manual switching mode when the auto_man[1:0] field is set to manual via pin, then the IDT8T49N205I will use the clk_sel input pin to determine which input to use as a reference. similarly, if set to manual via register, then the device will use the clk_sel register bit to determine the input reference. in either case, the pll will lock to the selected reference if there is a valid clock present on that input. if there is not a valid clock present on the selected input, the IDT8T49N205I will go into holdover (low bandwidth frequency translator mode) or free-run (high bandwidth frequency translator mode) state. in either case, the holdover alarm will be raised. this will occur even if there is a valid clock on the non-selected reference input. the device will recover from holdover / free-run state once a valid clock is re-established on the selected reference input. the IDT8T49N205I will only switch input references on command from the user. the user must either change the clk_sel register bit (if in manual via register) or clk_sel input pin (if in manual via pin). automatic switching mode when the auto_man[1:0] field is set to either of the automatic selection modes (revertive or non-revertive), the IDT8T49N205I determines which input reference it prefers / starts from by the state of the clk_sel register bit only. the clk_sel input pin is not used in either automatic switching mode. when starting from an unlocked condit ion, the device will lock to the input reference indicated by the clk_sel register bit. it will not pay attention to the non-selected input reference until a locked state has been achieved. this is necessary to prevent ?hunting? behavior during the locking phase. once the IDT8T49N205I has achieved a stable lock, it will remain locked to the preferred input reference as long as there is a valid clock on it. if at some point, that clock fails, then the device will automatically switch to the other input reference as long as there is a valid clock there. if there is not a valid clock on either input reference, the IDT8T49N205I will go into holdover (low bandwidth frequency translator mode) or free-run (high bandwidth frequency translator mode) state. in either case, the holdover alarm will be raised. the device will recover from holdover / free-run state once a valid clock is re-established on either reference input. if clocks are valid on both input references, the device will choose the reference indicated by the clk_sel register bit. if running from the non-preferred input reference and a valid clock returns, there is a difference in behavior between revertive and non-revertive modes. in revertive mode, the device will switch back to the reference indicated by the clk_sel register bit even if there is still a valid clock on the non-preferred reference input. in non-revertive mode, the IDT8T49N205I will not switch back as long as the non-preferred input reference still has a valid clock on it. switchover behavior of the pll even though the two input references have the same nominal frequency, there may be minor differences in frequency and potentially large differences in phase between them. the IDT8T49N205I has two options: phase build-out or phase-slope limiting to determine how it will adjust its output to the new input reference when operating in low-bandwidth mode. only phase-slope limiting is available in high-bandwidth mode. the pbo_disable bit is used to deter mine which method is used in low_bandwidth mode. in phase slope limiting operation, the IDT8T49N205I will adjust the output phase at a fixed maximum rate until the output phase and frequency are now aligned to the new input reference. phase will always be adjusted so that no unacceptably short clock periods are generated on the output of the id t8t49n205i. please contact idt if more information on the maximum phase slope adjustment rate is needed. in phase build-out operation, the device will absorb most of the phase difference between the two inputs (or between the input and current vco setting if recovering from holdover). please refer to
idt8t49n205anlgi revision b july 9, 2013 8 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out table 6 for exact limits. any phase difference that is not absorbed will be reflected on the output at the same maximum rate as in phase slope limiting operation. holdover / free-run behavior when both input references have failed (automatic mode) or the selected input has failed (manual mode), the IDT8T49N205I will enter holdover (low bandwidth frequency translator mode) or free-run (high bandwidth frequency translator mode) state . if operating in low bandwidth frequency translation mode, the pll will continue to reference itself to the local oscillator and will hold its output phase and frequency in relation to that source. output stability is determined by the stability of th e local oscillator in this case. however, if operating in high bandwidth frequency translation mode, the pll no longer has any frequency reference to use and the vco will return to the center of its tuning range. similarly, if operating in low-bandwidth mode and no initial frequency lock has been achieved, the vco will stay at or return to the center of its tuning range. if the device is programmed to perform manual switching, once the selected input reference recovers, the IDT8T49N205I will switch back to that input reference. if programmed for either automatic mode, the device will switch back to whichever input reference has a valid clock first. the switchover that results from re turning from holdover or free-run is handled in the same way as a switch between two valid input references as described in the previous section. output configuration the two outputs of the IDT8T49N205I both provide the same clock frequency. both must operate from the same output voltage level of 3.3v or 2.5v, although this output voltage may be less than or equal to the core voltage (3.3v or 2.5v) the rest of the device is operating from. the output voltage level used on the two outputs is supplied on the v cco pin. the two outputs are in dividually selectable as lvds or lvpecl output types via the q0_type and q1_type register bits. these two selection bits are provided in each configuration to allow different output type settings under each configuration. the two outputs can be enabled individually also via both register control bits and input pins. when both the oen register bit and oen pin are enabled, then the appropriate output is enabled. the oen register bits default to enabled so that by default the outputs can be directly controlled by the input pi ns. similarly, the input pins are provisioned with weak pull-ups so t hat if they are left unconnected, the output state can be directly controlled by the register bits. when the differential output is in the disabled state, it will show a high impedance condition.
idt8t49n205anlgi revision b july 9, 2013 9 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out serial interface configuration description the IDT8T49N205I has an i 2 c-compatible configuration interface to access any of the internal registers (table 4d) for frequency and pll parameter programming. the idt8t4 9n205i acts as a slave device on the i 2 c bus and has the address 0b11011xx, where xx is set by the values on the s_a0 & s_a1 pins (see table 4a for details). the interface accepts byte-oriented block write and block read operations. an address byte (p) specifies the register address (table 4d) as the byte position of the first register to write or read. data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first, see table 4b, 4c). read and write block transfers can be stopped after any complete byte transfer. it is recommended to terminate i 2 c the read or write transfer after accessing byte #23. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-up resistors have a size of 50k ? typical. note: if a different device slave address is desired, please contact idt. table 4a. i 2 c device slave address table 4b. block write operation table 4c. block read operation 11011s_a1s_a0r/w bit 1 2:8 9 10 11:18 19 20:27 28 29-36 37 ... ... ... description start slave address w (0) ack address byte (p) ack data byte (p) ack data byte (p+1) ack data byte ... ack stop length (bits) 1711818181811 bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39-46 47 ... ... ... description start slave address w (0) a c k address byte (p) a c k repeate d start slave address r (1) a c k data byte (p) a c k data byte (p+1) a c k data byte ... a c k stop length (bits) 1711811 7118181811
idt8t49n205anlgi revision b july 9, 2013 10 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out register descriptions please consult idt for configuration software and/or programming gui des to assist in selection of optimal register settings for the desired configurations. table 4d. i 2 c register map register bit color key reg binary register address register bit d7 d6 d5 d4 d3 d2 d1 d0 0 00000 mfrac0[17] mfrac0[16] mfrac0[15] mfrac0[14] mfrac0[13] mfrac0[12] mfrac0[11] mfrac0[10] 1 00001 mfrac1[17] mfrac1[16] mfrac1[15] mfrac1[14] mfrac1[13] mfrac1[12] mfrac1[11] mfrac1[10] 2 00010 mfrac0[9] mfrac0[8] mfrac0[7] mfrac0[6] mfrac0[5] mfrac0[4] mfrac0[3] mfrac0[2] 3 00011 mfrac1[9] mfrac1[8] mfrac1[7] mfrac1[6] mfrac1[5] mfrac1[4] mfrac1[3] mfrac1[2] 4 00100 mfrac0[1] mfrac0[0] mint0[7] mint0[6] mint0[5] mint0[4] mint0[3] mint0[2] 5 00101 mfrac1[1] mfrac1[0] mint1[7] mint1[6] mint1[5] mint1[4] mint1[3] mint1[2] 6 00110 mint0[1] mint0[0] p0[16] p0[15] p0[14] p0[13] p0[12] p0[11] 7 00111 mint1[1] mint1[0] p1[16] p1[15] p1[14] p1[13] p1[12] p1[11] 8 01000 p0[10] p0[9] p0[8] p0[7] p0[6] p0[5] p0[4] p0[3] 9 01001 p1[10] p1[9] p1[8] p1[7] p1[6] p1[5] p1[4] p1[3] 10 01010 p0[2] p0[1] p0[0] m1_0[16] m1_0[15] m1_0[14] m1_0[13] m1_0[12] 11 01011 p1[2] p1[1] p1[0] m1_1[16] m1_1[15] m1_1[14] m1_1[13] m1_1[12] 12 01100 m1_0[11] m1_0[10] m1_0[9] m1_0[8] m1_0[7] m1_0[6] m1_0[5] m1_0[4] 13 01101 m1_1[11] m1_1[10] m1_1[9] m1_1[8] m1_1[7] m1_1[6] m1_1[5] m1_1[4] 14 01110 m1_0[3] m1_0[2] m1_0[1] m1_0[0] n0[10] n0[9] n0[8] n0[7] 15 01111 m1_1[3] m1_1[2] m1_1[1] m1_1[0] n1[10] n1[9] n1[8] n1[7] 16 10000 n0[6] n0[5] n0[4] n0[3] n0[2] n0[1] n0[0] bw0[6] 17 10001 n1[6] n1[5] n1[4] n1[3] n1[2] n1[1] n1[0] bw1[6] 18 10010 bw0[5] bw0[4] bw0[3] bw0[2] bw0[1] bw0[0] q1_type0 q0_type0 19 10011 bw1[5] bw1[4] bw1[3] bw1[2] bw1[1] bw1[0] q1_type1 q0_type1 20 10100 mode_sel[1] mode_sel[0] config cfg_pin_reg oe1 oe0 rsvd rsvd 21 10101 clk_sel auto_man[1] auto_man[0] 0 adc_rate[1] adc_rate[0] lck_win[1] lck_win[0] 22 10110 1 0 1 0 dbl_xtal 0 pbo_disable 1 23 10111 clk_active holdover clk1bad clk0bad xtal_bad lock_ind rsvd rsvd configuration 0 specific bits configuration 1 specific bits global control & status bits
idt8t49n205anlgi revision b july 9, 2013 11 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out the register bits described in table 4e are duplicated, with one set applying for configuration 0 and th e other for configuration 1. the functions of the bits are identical, but only apply when the configuration they apply to is enabled. replace the lowercase n in the bit field description with 0 or 1 to find the field?s location in the bitmap in table 4d. table 4e. configuration-specific control bits table 4f. global control bits register bits function q0_typen determines the output type for output pair q0, nq0 for configuration n. 0 = lvpecl 1 = lvds q1_typen determines the output type for output pair q1, nq1 for configuration n. 0 = lvpecl 1 = lvds pn[16:0] reference pre-divider for configuration n. m1_n[16:0] integer feedback divider in lower feedback loop for configuration n. m_intn[7:0] feedback divider, integer value in upper feedback loop for configuration n. m_fracn[17:0] feedback divider, fractional value in upper feedback loop for configuration n. nn[10:0] output divider for configuration n. bwn[6:0] internal operation settings for configuration n. please use idt IDT8T49N205I configuration software to de termine the correct settings for these bits for the specific configuration. alternatively, please consult with id t directly for further information on the functions of these bits.the function of these bits are explained in tables 4j and 4k. register bits function mode_sel[1:0] pll mode select 00 = low bandwidth frequency translator 01 = frequency synthesizer 10 = high bandwidth frequency translator 11 = high bandwidth frequency translator cfg_pin_reg configuration control. select s whether the configuration selection function is under pin or register control. 0 = pin control 1 = register control config configuration selection. selects whether the device uses t he register configuration set 0 or 1. this bit only has an effect when the config_pin_reg bit is set to 1 to enable register control. oe0 output enable control for output 0. both this register bit and the corresponding output enable pin oe0 must be asserted to enable the q0, nq0 output. 0 = output q0, nq0 disabled 1 = output q0, nq0 under control of the oe0 pin oe1 output enable control for output 1. both this register bit and the corresponding output enable pin oe1 must be asserted to enable the q1, nq1 output. 0 = output q1, nq1 disabled 1 = output q1, nq1 under control of the oe1 pin rsvd reserved bits - user should write a ?0? to these bit positions if a write to these registers is needed auto_man[1:0] selects how input clock selection is performed. 00 = manual selection via pin only 01 = automatic, non-revertive 10 = automatic, revertive 11 = manual selection via register only
idt8t49n205anlgi revision b july 9, 2013 12 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out table 4g. global status bits table 4h. bw[6:0] bits clk_sel in manual clock selection via register mode, this bit w ill command which input clock is selected. in the automatic modes, this indicates the primary clock input. in manual selection via pin mode, this bit has no effect. 0 = clk0 1 = clk1 adc_rate[1:0] sets the adc sampling rate in low-bandwidth mo de as a fraction of the crystal input frequency. 00 = crystal frequency / 16 01 = crystal frequency / 8 10 = crystal frequency / 4 (recommended) 11 = crystal frequency / 2 lck_win[1:0] sets the width of the window in which a new reference edge must fall relative to the feedback edge: 00 = 125nsec (recommended), 01 = 500nsec, 10 = 2 ? sec, 11 = 8 ? sec pbo_disable disables the use of phase build-out when switching between inputs: 0 = pbo enabled 1 = pbo disabled and only phase-slope limiting used dbl_xtal when set, this bit will double the frequency of the cryst al input before applying it to the phase-frequency detector. register bits function clk0bad status bit for input clock 0. this function is mirrored in the clk0bad pin. 0 = input 0 good 1 = input 0 bad. self clears when input clock returns to good status clk1bad status bit for input clock 1. this function is mirrored in the clk1bad pin. 0 = input 0 good 1 = input 0 bad. self clears when input clock returns to good status xtalbad status bit. this function is mirrored on the xtalbad pin. 0= crystal input good 1 = crystal input bad. self-clears when the xtal clock returns to good status lock_ind status bit. this function is mirrored on the lock_ind pin. 0 = pll unlocked 1 = pll locked holdover status bit. this function is mirrored on the holdover pin. 0 = input to phase detector is within specifications and device is tracking to it 1 = phase detector input not wit hin specifications and dcxo is frozen at last value clk_active status bit. indicates which input clock is active. automa tically updates during fail-over switching. status also indicated on clk_active pin. mode bw[6] bw[5] bw[4] bw[3] bw[2] bw[1] bw[0] synthesizer mode pll2_lf[1] pll2_lf[0] dsm_o rd dsm_en pll2_cp[1] pll2_cp[0] pll2_low_icp high-bandwidth mode pll2_lf[1] pll2_lf[0] dsm_o rd dsm_en pll2_cp[1] pll2_cp[0] pll2_low_icp low-bandwidth mode adc_gain[3] adc_gain[2] adc_ga in[1] adc_gain[0] pll1_cp[1] pll1_cp[0] pll2_low_icp
idt8t49n205anlgi revision b july 9, 2013 13 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out table 4i. functions of fields in bw[6:0] table 4j. upper loop (pll2) bandwidth settings note: to achieve 4mhz bandwidth, reference to the phase detector should be 80mhz. register bits function pll2_lf[1:0] sets loop filter values for upper loop pll in frequency synthesizer & high-bandwidth modes. defaults to setting of 00 when in low bandwidth mode. see table 4l for settings. dsm_ord sets delta-sigma modulation to 2nd (0) or 3rd order (1) operation dsm_en enables delta-sigma modulator 0 = disabled - feedback in integer mode only 1 = enabled - feedback in fractional mode pll2_cp[1:0] upper loop pll charge pump current settings: 00 = 173 ? a (defaults to this setting in low bandwidth mode) 01 = 346 ? a 10 = 692 ? a 11 = reserved pll2_low_icp reduces charge pump current by 1/3 to reduce bandwidth variations resulting from higher feedback register settings or high vco operating frequency (>2.4ghz). adc_gain[3:0] gain setting for adc in low bandwidth mode. pll1_cp[1:0] lower loop pll charge pump current settings (lower loop is only used in low bandwidth mode): 00 = 800 ? a 01 = 400 ? a 10 = 200 ? a 11 = 100 ? a desired bandwidth pll2_cp pll2_low_icp pll2_lf frequency synthesizer mode 200khz 00 1 00 400khz 01 1 01 800khz 10 1 10 2mhz 10 1 11 high bandwidth frequency translator mode 200khz 00 1 00 400khz 01 1 01 800khz 10 1 10 4mhz 10 0 11
idt8t49n205anlgi revision b july 9, 2013 14 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 5a. lvpecl power supply dc characteristics, v cc = v cco = 3.3v5%, v ee = 0v, t a = -40c to 85c table 5b. lvpecl power supply dc characteristics, v cc = 3.3v5%, v cco = 2.5v5%, v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc 3.6v inputs, v i xtal_in other inputs 0v to 2v -0.5v to v cc + 0.5v outputs, v o (lvcmos) -0.5v to v cco + 0.5v outputs, i o (lvpecl) continuous current surge current 50ma 100ma outputs, i o (lvds) continuous current surge current 10ma 15ma package thermal impedance, ? ja 32.4 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.30 3.3 v cc v v cco output supply voltage 3.135 3.3 3.465 v i ee power supply current 320 ma i cca analog supply current 30 ma symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.30 3.3 v cc v v cco output supply voltage 2.375 2.5 2.625 v i ee power supply current 320 ma i cca analog supply current 30 ma
idt8t49n205anlgi revision b july 9, 2013 15 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out table 5c. lvpecl power supply dc characteristics, v cc = v cco = 2.5v5%, v ee = 0v, t a = -40c to 85c table 5d. lvds power supply dc characteristics, v cc = v cco = 3.3v5%, t a = -40c to 85c table 5e. lvds power supply dc characteristics, v cc = 3.3v5%, v cco = 2.5v5%, t a = -40c to 85c table 5f. lvds power supply dc characteristics, v cc = v cco = 2.5v5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 2.375 2.5 2.625 v v cca analog supply voltage v cc ? 0.26 2.5 v cc v v cco output supply voltage 2.375 2.5 2.625 v i ee power supply current 304 ma i cca analog supply current 26 ma symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.30 3.3 v cc v v cco output supply voltage 3.135 3.3 3.465 v i cc power supply current 273 ma i cca analog supply current 30 ma i cco output supply current 42 ma symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.30 3.3 v cc v v cco output supply voltage 2.375 2.5 2.625 v i cc power supply current 273 ma i cca analog supply current 30 ma i cco output supply current 42 ma symbol parameter test conditions minimum typical maximum units v cc core supply voltage 2.375 2.5 2.625 v v cca analog supply voltage v cc ? 0.26 2.5 v cc v v cco output supply voltage 2.375 2.5 2.625 v i cc power supply current 263 ma i cca analog supply current 26 ma i cco output supply current 42 ma
idt8t49n205anlgi revision b july 9, 2013 16 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out table 5g. lvcmos/lvttl dc characteristics, t a = -40c to 85c table 5h. differential dc characteristics, v cc = v cco = 3.3v5% or 2.5v5%, v ee = 0v, t a = -40c to 85c note 1: common mode input voltage is defined as the crosspoint voltage. table 5i. lvpecl dc characteristics, v cc = v cco = 3.3v5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cco ? 2v. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v cc = 3.3v 2.2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v i ih input high current clk_sel, config, pll_bypass, s_a[1:0] v cc = v in = 3.465v or 2.625v 150 a oe0, oe1, sclk, sdata v cc = v in = 3.465v or 2.625v 5 a i il input low current clk_sel, config, pll_bypass, s_a[1:0] v cc = 3.465v or 2.625v, v in = 0v -5 a oe0, oe1, sclk, sdata v cc = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage holdover, sdata clk_active, lock_ind, xtalbad, clk0bad, clk1bad v cc = 3.465v, i oh = -8ma 2.6 v v cc = 2.625v, i oh = -8ma 1.8 v v ol output low voltage holdover, sdata clk_active, lock_ind, xtalbad, clk0bad, clk1bad v cc = 3.465v or 2.625v, i ol = 8ma 0.5 v symbol parameter test conditio ns minimum typical maximum units i ih input high current clk0, nclk0, clk1, nclk1 v cc = v in = 3.465v or 2.625v 150 a i il input low current clk0, clk1 v cc = 3.465v or 2.625v, v in = 0v -5 a nclk0, nclk1 v cc = 3.465v or 2.625v, v in = 0v -150 a v pp peak-to-peak voltage 0.15 1.3 v v cmr common mode input voltage; note 1 v ee + 0.5 v cc ? 1.0 v symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cco ? 1.1 v cco ? 0.7 v v ol output low voltage note 1 v cco ? 2.0 v cco ? 1.5 v v swing peak-to-peak output voltage swing 0.6 1.0 v
idt8t49n205anlgi revision b july 9, 2013 17 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out table 5j. lvpecl dc characteristics, v cc = 3.3v5% or 2.5v5%, v cco = 2.5v5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cco ? 2v. table 5k. lvds dc characteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 5l. lvds dc characteristics, v cc = 3.3v 5% or 2.5v5%, v cco = 2.5v5%, v ee = 0v, t a = -40c to 85c table 6. input frequency characteristics, v cc = v cco = 3.3v 5%, t a = -40c to 85c note 1: for the input crystal and clkx, nclkx frequency range, the m value must be set for t he vco to operate within the 1995mh z to 2600mhz range. table 7. crystal characteristics symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cco ? 1.1 v cco ? 0.7 v v ol output low voltage note 1 v cco ? 2.0 v cco ? 1.5 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.375 v ? v os v os magnitude change 50 mv symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.375 v ? v os v os magnitude change 50 mv symbol parameter test conditio ns minimum typical maximum units f in input frequency xtal_in, xtal_out note 1 16 40 mhz clk0, nclk0, clk1, nclk1 high bandwidth mode 16 710 mhz low bandwidth mode 0.008 710 mhz sclk 5mhz parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 16 40 mhz equivalent series resistance (esr) 100 ? shunt capacitance 7pf
idt8t49n205anlgi revision b july 9, 2013 18 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out ac electrical characteristics table 8. ac characteristics, v cc = v cco = 3.3v5% or 2.5v5%, or v cc = 3.3v5%, v cco = 2.5v5% (lvpecl only), v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium symbol parameter test conditio ns minimum typical maximum units f out output frequency 0.98 1300 mhz f vco vco frequency 1995 2600 mhz t jit(?) rms phase jitter; integer divide ratio synth mode (integer fb), f out = 400mhz, 40mhz xtal, integration range: 12khz ? 40mhz 245 385 fs synth mode (fracn fb), f out = 698.81mhz, 40mhz xtal, integration range: 12khz ? 20mhz 355 605 fs lvds output (note 1), hbw mode, f in = 133.33mhz, f out = 400mhz, integration range: 12khz ? 20mhz 320 460 fs lvpecl output, lbw mode (fracn), 40mhz xtal, f in = 10mhz, f out = 155.52mhz, integration range: 12khz ? 20mhz 379 610 fs lvpecl output, lbw mode (fracn), 40mhz xtal, f in = 25mhz, f out = 161.1328125mhz, integration range: 12khz ? 20mhz 396 650 fs t jit(cc) cycle-to-cycle jitter; note 2, 5 frequency synthesizer mode 40 ps frequency translator mode 40 ps t sk(o) output skew; note 2, 3, 5 35 ps t jit(per) rms period jitter; note 5 lvpecl outputs 2.0 6.5 ps lvds outputs 2.0 4.5 ps t err initial phase error f in0 = 8khz, f in1 = 8khz with 40usec phase offset, low-bandwidth mode 4.5 ns t pwl switchover phase slope high-bandwidth mode, 800khz loop bw; f out = 100mhz, 4s phase error 1.5 ms / s t r / t f output rise/fall time; note 5 lvpecl outputs 20% to 80% 95 485 ps lvds outputs 20% to 80% 128 498 ps odc output duty cycle; note 5 lvpecl outputs f out < 600mhz 47 53 % lvds outputs f out ? 600mhz 45 55 % t set output re-configuration settling time note 4 from falling edge of the 8th sclk for a register change 200 ns from edge on config pin 10 ns
idt8t49n205anlgi revision b july 9, 2013 19 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out has been reached under these conditions. note 1: measured using a rohde & schwarz sma100 signa l generator, 9khz to 6ghz as the input source. note 2: this parameter is defined in accordance with jedec standard 65. note 3: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the output diffe rential cross points. note 4: this settling time does not include pll re-calibration and locking if required. since those times are highly dependent on the specific configuration, please contact idt for ti mes if pll re-configuration is perform ed as part of the configuration change. note 5: measurements are collected with the following output frequencies: 19.44mhz, 38.88mhz, 66.6667mhz, 125mhz, 156.25mhz, 161.1328125mhz, 311.04mhz, 400mhz, 480mhz, 622.08mhz 1000mhz, 1200mhz, 1300mhz.
idt8t49n205anlgi revision b july 9, 2013 20 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out typical phase noise at 400mhz (3.3v) noise power (dbc / hz) offset frequency (hz)
idt8t49n205anlgi revision b july 9, 2013 21 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out parameter measureme nt information 3.3 core/3.3v lvpecl output load test circuit 3.3 core/2.5v lvpecl output load test circuit 2.5 core/2.5v lvds output load test circuit 2.5 core/2.5v lvpecl outp ut load test circuit 3.3 core/3.3v lvds output load test circuit 3.3 core/2.5v lvds output load test circuit v cc, 2v -1.3v+0.165v v cco v cca 2v scope qx nqx v ee v cc 2.8v0.04v -0.5v0.125v v cca 2v 2.8v0.04v v cco scope qx nqx 2.5v5% power supply +? float gnd v cc, v cco v cca v cc, 2v -0.5v0.125v v cca 2v v cco v cca v cco v cc, qx nqx flo a t gnd ++ ? power s upply s cope 2.5v5% 3.3v5% v v v
idt8t49n205anlgi revision b july 9, 2013 22 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out parameter measurement in formation, continued differential input levels cycle-to-cycle jitter lvds output rise/fall time output skew rms period jitter lvpecl output rise/fall time v cc v ee clkx nclkx t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles nqx qx 20% 80% 80% 20% t r t f v od nqx qx qx qy nqx nqy v oh v ref v ol t jit (per) = (t per(n) ? t per me a n) 2 / (n ? 1) t per(n) n = 1...10000 cycle s 10000 n = 1 nqx qx
idt8t49n205anlgi revision b july 9, 2013 23 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out parameter measurement in formation, continued offset voltage setup differential output duty cycle/output pulse width/period rms phase jitter differential output voltage setup nqx qx
idt8t49n205anlgi revision b july 9, 2013 24 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out applications information recommendations for unused input and output pins inputs: clkx/nclkx inputs for applications not requiring the use of either differential input, both clkx and nclkx can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clkx to ground. it is recommended that clkx, nclkx be left unconnected in frequency synthesizer mode. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl output pairs c an be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating there should be no trace attached. lvcmos outputs all unused lvcmos outputs can be left floating. there should be no trace attached. recommended values for low- bandwidth mode loop filter external loop filter components are not needed in frequency synthesizer or high-bandwidth modes. in low-bandwidth mode, the loop filter structure and components shown in figure 11 are recommended. please consult id t if other values are needed.
idt8t49n205anlgi revision b july 9, 2013 25 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out wiring the differential input to accept single-ended levels figure 4 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requi res that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 4. recommended schematic for wiring a diff erential input to accept single-ended levels rec eiv er + - r4 10 0 r3 10 0 rs zo = 50 ohm ro driv er vcc vcc r2 1k r1 1k c1 0.1uf ro + rs = zo v1 vc c vc c
idt8t49n205anlgi revision b july 9, 2013 26 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 5a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 5b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 5a. general diagram for lvcmos driver to xtal input interface figure 5b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
idt8t49n205anlgi revision b july 9, 2013 27 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out differential clock input interface the clk /nclk accepts lvds, l vpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 6a to 6e show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver co mponent to confirm the driver termination requirements. for example, in figure 8a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 6a. clk/nclk input driven by an idt open emitter lvhstl driver figure 6c. clk/nclk input driven by a 3.3v lvpecl driver figure 6e. clk/nclk input driven by a 3.3v hcsl driver figure 6b. clk/nclk input driven by a 3.3v lvpecl driver figure 6d. clk/nclk input driven by a 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input 3 . 3v c l k n c l k 3 . 3v 3 . 3v lvpe cl differential in p u t h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t clk nclk differential input lvpecl 3.3v zo = 50 zo = 50 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 zo = 50
idt8t49n205anlgi revision b july 9, 2013 28 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 7a can be used with either type of output structure. figure 7b , which can also be used with both output types, is an op tional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds termination lv d s driver lv d s driver lv d s receiver lv d s receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 7a. standard termination figure 7b. optional termination
idt8t49n205anlgi revision b july 9, 2013 29 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 8a and 8b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 8a. 3.3v lvpecl output termination figure 8b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
idt8t49n205anlgi revision b july 9, 2013 30 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out termination for 2.5v lvpecl outputs figure 10a and figure 9b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cco ? 2v. for v cco = 2.5v, the v cco ? 2v is very close to ground level. the r3 in figure 9b can be eliminated and the termination is shown in figure 9c. figure 9a. 2.5v lvpecl driver termination example figure 9c. 2.5v lvpecl driver termination example figure 9b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cco = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ?
idt8t49n205anlgi revision b july 9, 2013 31 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 10. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance lead frame base package, amkor technology. figure 10. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
idt8t49n205anlgi revision b july 9, 2013 32 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out schematic layout figure 11 (next page), shows an example of the uft (8t49n205) application schematic. input and ou tput terminations shown are intended as examples only and may not represent the exact user configuration. refer to the pin description and functional tables in the datasheet to ensure the logic c ontrol inputs are properly set. in this example, the device is operated at v cc =3.3v. for 2.5v option, please refer to the ?termination fo r 2.5v lvpecl outputs? for output termination recommendation. a 12pf parallel resonant fox fx325bs series 16mhz to 40mhz crystal is used in this example. different crystal frequencies may be used. the c1 = c2 = 5pf are recommended for frequency accuracy. if different crystal types are used, please consult idt for recommendations. for different board layout, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. it is recommended that the loop filter components be laid out for the 3-pole option. this will also allow either 2-pole or 3-pole filter to be used. the 3-pole filter can be used for additional spur reduction. if a 2- pole filter construction is used, the lf0 and lf1 pins must be tied-together and to the filter. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the uft (8t49n205) provides separate v cc , v cca and v cco power supplies to isolate any high switching noise from coupling into the internal pll. in order to achieve the best possible filtering, it is highly recommended that the 0.1f capacitors on the device side of the ferrite beads be placed on the device side of the pcb as close to the power pins as possible. this is represented by the placement of these capacitors in the sc hematic. if space is lim ited, the ferrite beads and 10f capacitors connected to 3. 3v can be placed on the opposite side of the pcb. if space permits, place all filter components on the device side of the board. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of noise frequencies. this low-pass filter starts to atte nuate noise at approximately 10 khz. if a specific frequency noise compone nt is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk c apacitance in the local area of all devices.
idt8t49n205anlgi revision b july 9, 2013 33 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out figure 11. IDT8T49N205I application schematic + - c2 5pf r1 100 x1 16mhz to 40mhz zo = zo_diff = 100-ohm c1 5pf to logic i n pu t p i ns set logic input to '0' logic in put pin exam ples to logic input pins set logic input to '1' 1 2 p f ru 2 no t ins t alled ru 1 1k rd 2 1k rd 1 not installed vc c vc c r2 10 vc c o c12 0. 1 uf c11 10uf c9 10uf c8 0.1uf c10 0.1uf vc c 3. 3 v fb2 m ur a ta , bl m18 bb2 2 1sn 1 fb1 m ur a ta , bl m18 bb2 2 1sn 1 vcc (note 2) (note 2) uft u2 xtal_in 1 xtal_out 2 cl k_ sel 4 cl k0 5 cl k0 6 cl k1 9 cl k1 10 pl l_ by pass 12 s_ a0 18 s_ a1 17 sc lk 15 sd ata 14 co n f i g 16 q0 27 q0 26 oe0 28 q1 24 q1 23 oe1 22 lock_ind 30 c lk_a cti ve 31 h o ld o ver 37 cl k0 bad 38 cl k1 bad 39 xtal bad 40 lf1 34 lf0 33 vc c o 25 vcc 3 vc c 7 vc c 13 vcc 29 vc c a 36 vee 8 vee 21 vee 35 nc 19 nc 20 nc 11 nc 32 (note 1) (note 1) (note 1) (note 1) (note 1) rs 470k r3 220k cp 0.001uf lock_ ind cs 1u f c3 0.001uf note 1: ce0, oe1, clk_sel, pll_bypass, s_a0 and s_a1 are digital control input s. if external pull-up/down needed, see "logic input pin examples" shown at left. please note t hat oe0 and oe1 are internally pulled up so no external pull-ups are required to enable them. r5 100 nc l k 0 cl k0 r9 125 r14 84 r10 125 r1 5 84 cl k1 nc l k 1 r17 125 r6 84 r4 125 r7 84 + - rs 1 4 70 k cp 1 0 . 00 1u f cs1 1uf zo = 50-ohm lf0 zo = 50-ohm lf1 outp ut t ermi nati on e xamp le - lvpe cl o utpu t sh own (not e 3) o utpu t te rmina tion exa mple - l vds outp ut sh own (not e 3) 3-pole loop filter 2- po l e l o op fi l t er - (o pt io n al ) s_a0 p ll _ byp ass s_a1 c l k_ sel config ho ldover clk_active clk1bad clkbad oe1 oe0 xtalbad (note 1) (note 1) note 2: clk_sel, pll_bypass and config are internally pulled down. no external compononents required to select default condition. notes (note 2) note 3: other configurations are supported. please contact idt for details. l vds input t ermi natio n e xamp le - ( note 3) vcc vcco c4 0. 1u f c5 0. 1 uf c6 0.1uf c7 0.1uf r1 1 4. 7 k r12 4.7k sda ta scl k c14 10uf c1 3 0.1uf c15 0.1uf 3. 3 v fox fx325bs l vpec l inp ut t ermi natio n e xamp le - ( note 3) vc c
idt8t49n205anlgi revision b july 9, 2013 34 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out lvpecl power considerations this section provides information on power dissipati on and junction temperature for the IDT8T49N205I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT8T49N205I is the sum of the core power plus the output power dissipated due to loading. the following is the output power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating output power dissipated due to loading. ? power (core) max = v cc_max * i ee_max = 3.465v * 320ma = 1108.8w ? power (outputs) max = 33.2mw/loaded output pair if all outputs are loaded, the total power is 2 * 33.2mw = 66.4mw total power_ max (3.465v, with all outputs s witching) = 1108.8mw + 66.4mw = 1175.2mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 32.4c/w per table 9 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.175w * 32.4c/w = 123.1c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 9. thermal resistance ? ja for 40 lead vfqfn, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 32.4c/w 25.7c/w 23.4c/w
idt8t49n205anlgi revision b july 9, 2013 35 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pairs. lvpecl output driver circuit and termination are shown in figure 12. figure 12. lvpecl driver circuit and termination to calculate output power dissipation due to loadin g, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.7v (v cco_max ? v oh_max ) = 0.7v ? for logic low, v out = v ol_max = v cco_max ? 1.5v (v cco_max ? v ol_max ) = 1.5v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.7v)/50 ? ] * 0.7v = 18.2mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l] * (v cco_max ? v ol_max ) = [(2v ? 1.5v)/50 ? ] * 1.5v = 15mw total power dissipation per output pair = pd_h + pd_l = 33.2mw v out v cco v cco - 2v q1 rl 50
idt8t49n205anlgi revision b july 9, 2013 36 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out lvds power considerations this section provides information on power dissipati on and junction temperature for the IDT8T49N205I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT8T49N205I is the sum of the core power plus the output power dissipation due to the load . the following is the output power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v cc_max * (i cc_max + i cca_max ) = 3.465v * (273ma + 30ma) = 1049.895mw ? power (outputs) max = v cco_max * i cco_max = 3.465v * 42ma = 145.53mw total power_ max = 1049.895mw + 145.53mw = 1195.425mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate va lue is 32.4c/w per table 10 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.195w * 32.4c/w = 123.7c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 10. thermal resistance ? ja for 40 lead vfqfn, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 32.4c/w 25.7c/w 23.4c/w
idt8t49n205anlgi revision b july 9, 2013 37 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out reliability information table 11. ? ja vs. air flow table for a 40 lead vfqfn transistor count the transistor count for IDT8T49N205I is: 53,727 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 32.4c/w 25.7c/w 23.4c/w
idt8t49n205anlgi revision b july 9, 2013 38 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out 40 lead vfqfn package out line and package dimensions
idt8t49n205anlgi revision b july 9, 2013 39 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out 40 lead vfqfn package outline an d package dimensions, continued 40 lead vfqfn, d2/e2 epad dimensions: 4.65mm x 4.65mm
idt8t49n205anlgi revision b july 9, 2013 40 ?2013 integrated device technology, inc. IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out ordering information table 12. ordering information note: for the specific -ddd order codes, refer to femtoclock ng universal frequency tran slator ordering product information document. part/order number marking package shipping packaging temperature 8t49n205a-dddnlgi idt8t49n205a-dddnlg i ?lead-free? 40 lead vfqfn tray -40 ? c to +85 ? c 8t49n205a-dddnlgi8 idt8t49n205a-dddnlgi ?lead-free? 40 lead vfqfn tape & reel -40 ? c to +85 ? c
IDT8T49N205I data sheet femtocl ock? ng universal frequency tr anslator with phase build-out disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support sales netcom@idt.com +480-763-2056 we?ve got your timing solution

▲Up To Search▲

Price & Availability of IDT8T49N205I

	To Download IDT8T49N205I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .